As shown in FIG. 1, the conventional sense amplifier includes a data sensing circuitry 01, a dummy cell circuitry 02 and a differential amplifier 03. The data sensing circuitry 01 is a current detector; and the dummy cell circuitry 02 includes a dummy cell 021, a dummy multiplexer (YMUX) 022 and a current-voltage converting circuitry 023. More detailedly, the current detector 013 includes a NOR gate 0131, an NMOS 0132 and a PMOS 0133 providing a load effect, and the current-voltage convening circuitry 023 includes a NOR gate 0321, an NMOS 0232, and two PMOS 0233, 0234 providing a load effect, wherein the PMOS 0233, 0324 and the PMOS 0133 are identical in size.
The output node OP-SA of the data sensing circuitry 01 and the output node OP-DM of the dummy cell circuitry 02 are respectively electrically connected to two inputs 031, 032 of the amplifier 03 for comparing the output results in the outputs OP-SA and OP-DM to sense the data of selected cell in a memory array 011.
The memory array 011 includes plural memory cells kn . . . km . . . ln . . . lm etc., wherein the lines connect the drains of the vertical memory cells are bit lines BL-n . . . BL-m, and the lines connect the gates of the horizontal memory cells are word lines WL-k . . . WL-1. The bit lines BL-n, BL-m of the memory array 011 are electrically connected to a YMUX 012. One terminal of the transmission gate MUX-n (or MUX-m) of the YMUX 012 is electrically connected to the bit line BL-n (or BL-m) while the other terminal is electrically connected to the NMOS 0132 of the current detector 013.
When one memory cell of the memory array 011 (called the selected cell), e.g. the memory cell km, is to be read, an X-decoder and a Y-decoder (not shown) will execute a decoding function for obtaining an address of the memory cell km, and then enable word line WL-k and bit line BL-m. Now, the word line WL-k is called selected WL and the bit line BL-m is called selected BL. Thus, the output YSEL-m of the Y-decoder allows the corresponding transmission gate MUX-m of the YMUX 012 to be on in order that the data of the selected cell km can be sensed by the conventional sense amplifier through the bit line BL-m.
The dummy cell circuitry 02 is used for providing a reference voltage. When the input EN2 of the NOR gate 0231 is enabled, the dummy cell circuitry functions. If the gate of the dummy cell 021 is connected to VCC and the dummy cell 021 is biased with an operating point near to that of the selected cell kin, so the current of the dummy cell 021 and the current of the selected cell km which is allowed to be on are very close. The current of the dummy cell 012 is transmitted into the current-voltage converting circuit 023 through dummy YMUX 022, and there is the reference voltage, generated at the output OP-DM, which will then be transmitted into the input 031 of the differential amplifier 03.
When sensing the data in the selected cell km, we must maintain the bit line BL-m at a voltage near to the switching point, regardless of whether the selected cell km is an on cell or an off cell. Depending on whether the cell is on or off, the output OP-SA of detector 013 will have a small voltage swing. Then, the voltage at the output OP-SA is input to the input 032 of the differential amplifier 03 to be compared with the voltage at the output OP-DM in order that differential amplifier 03 can fast sense the data of the on cell or the off cell. It is to be noticed that the so-called switching point means the voltage at the bit line BL-m, when the voltage at the output node OP-DM equals to the voltage at the output node OP-DM. When the selected cell km is an on cell (having a low threshold voltage Vtn), there is a larger current flowing through current detector 013, the transmission gate MUX-m, and the selected cell km to the ground GND. Under a stable situation, the current flowing through the current detector 013 equals to the current flowing through the selected cell km and the value of this current is defined as Icell. When the selected cell km is an off cell (having a high threshold voltage Vtn), there is no or only a very small current flowing through said path.
When the input ENI of the NOR gate 0131 is enabled, the data sensing circuitry 01 begins to work. If the selected cell km is an off cell and the selected bit line BL-m has the lowest voltage, i.e. right at the beginning of being accessible, there is a current flowing from the Vcc of the PMOS 0133 and charging the equivalent capacitor of the selected bit line BL-m through NMOS 0132. Thus, the voltage of the bit line BL-m is higher and higher, and the NMOS is gradually cut-off. When the bit line BL-m is charged to have a voltage slightly higher than the switching point and the current through the current detector 013 is slightly smaller than one half of Icell, the voltage at the output node OP-SA is then higher than the voltage at the output node OP-DM, thus the differential amplifier 03 can correctly sense the data in the off cell. On the contrary, when the selected cell km is an on cell, the equivalent capacitor of the bit line BL-m will be discharged by the on cell with respect to the ground. Thus, the voltage at the bit line BL-m is lower and lower and the NMOS 0132 is turned on more and more. When the bit line BL-m is charged up to have a voltage slightly higher than the switching point and the current through the current detector 013 is larger than one half of Icell, the voltage at the output OP-SA is lower than the voltage at the output OP-DM, and then the differential amplifier 03 can correctly sense the data in the on cell.
There are three latent issues suffered by the conventional sense amplifier which are described as follows:
1) For obtaining a larger input voltage difference (i.e., larger than 0.4 V), the conventional sense amplifier usually applies the load device (i.e., PMOS 0133) with a relatively higher impedance (which is higher than that of the on cell). Therefore, when the off cell is to be sensed, the bit line BL-m cannot obtain a larger charging current (especially when the selected bit line has an initial grounded voltage), and thus the sensing speed is lowered.
2) If the conventional sense amplifier were designed to have a better noise immunity, the bit line (of the on cell or the off cell) should be kept at a marginal voltage with a certain amount from the switching point (usually for above about 100 mV). Because if their difference is too small, although the data in the cell can be fast sensed, the noise in GND or Vcc will result in an unstable bit line voltage which in turn results in an unstable output of current detector 013. Thus, the marginal voltage is normally designed to be somewhat distant form the switching point. In the case of WL-switching access, the previous selected cell and the present selected cell are to have the same bit line but the different word lines, and there is a relatively long delay time of the word line when an off cell is switched into an on cell, even if the data are sensed, the on cell is not completely turned on so that the equivalent current for charging (or discharging) the selected bit line is smaller than Icell. Thus, the conventional sense amplifier must take a relatively long period of time for allowing the bit line to be charged (or discharged) from the marginal voltage to the switching point.
3) When the NOR gate 0131 of the current detector 013 functions, whose trip voltage will vary with the noise-disturbed positive supply voltage Vcc and negative supply voltage Vss (not shown). When every selected cell is off, the voltage of the selected bit line will increase with the increase of the trip voltage.
When the trip voltage drops with the drop of the Vcc or the noise, but while there is no discharge path allowing the voltage of the selected bit line to drop, there are extra charges trapped in the selected bite line. Therefore, after the switch of the word line to the next selected on cell, it must take a relatively long period of time to discharge the extra charges to drop the voltage of the selected bit line below the switching point and thus the required sensing time is prolonged. Generally speaking, the noise signal can be over about 0.5 V, and the variation of the trip voltage can be over about 0.2 V so that for some short-time sensing applications, it is possible that before the sensing cycle ends, the extra bit line charges still cannot be discharged, and therefore the sensing errors are generated.
It is therefore attempted by the Applicant to deal with the above situation encountered by the prior art.